1. Field of the Invention
The invention relates to a signal display apparatus and an associated method, and more particularly, to a signal display apparatus and a method for storing a sequential data flow into shift registers of the signal display apparatus non-consecutively.
2. Description of the Prior Art
In modern information society, data is typically digitized into binary files for facilitating the processing of a huge amount of information via a semiconductor circuit. Each bit of data in the binary file is arranged in sequence to constitute a data flow so as to form the most fundamental digital data. Since the constituent bits of the digital data is arranged in a time sequence, a digital circuit is merely required to process a few bits of the sequential digital data at the same time. Thus, the design of the digital circuit can be substantially simplified and the layout dimensions of the digital circuit can be considerably reduced.
Among various types of digital circuits, a data register circuit for storing sequential data in a series manner is a fundamental constituent block. Please refer to FIG. 1. FIG. 1 is a function block diagram illustrating a combination of a conventional data register circuit 12 and a conventional interface circuit 10. The conventional interface circuit 10 has two output ends for outputting a sequential data signal 16 and a corresponding first clock 14, respectively. The data register circuit 12 is used to cooperate with the first clock 14 for storing the data signal 16 outputted from the interface circuit 10. The data register circuit 12 comprises two shift registers 18A and 18B with the same function, and which are referred to as the first shift register 18A and the second shift register 18B. Both of the shift registers 18A and 18B comprise a plurality of register units 19 which electrically connect to each other in a series manner. As shown in FIG. 1, four register units 19 are installed in the respective shift registers 18A, 18B for illustration. Each of the register units 19 is used to store a bit of data. The register unit 19 located on the right most side of the first shift register 18A is electrically connected to the register unit 19 located on the left most side of the second shift register 18B. Additionally, the first and second shift registers 18A and 18B have respective clock ends 22 for receiving triggers of the first clock 14 outputted from the interface circuit 10 to control operations of the first and second shift registers 18A and 18B.
The data register circuit 12 further comprises a display circuit 20 for displaying the sequential data stored in the data register unit 12. Explicitly speaking, the display circuit 20 has a plurality of display units 24, each of the display units 24 electrically connected to the corresponding register unit 19 for displaying the data in the corresponding register unit 19. The typical example of the display unit 19 is a light emitting diode (LED). The LED can be bright or dark depending on the conduction condition of the LED so as to represent the data of xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d stored in the corresponding register unit 19, respectively. The display circuit 20 has a variety of applications such as a network switch.
Since a plurality of terminals on the network exchange information with each other via the network switch, a display interface is required to display operational statuses of each of the terminals. A network administrator can thus conveniently monitor the operational statuses of each of the terminals on the network. For example, the network switch can utilize the circuit configuration shown in FIG. 1 to be the display interface. Under this situation, the four register units 19 of the first shift register 18A can be used to store four different types of the operational statuses for a first terminal. The operational statuses of a terminal could be the on-line status, the status of data transferring, the status of data collision, and so forth. Likewise, the second shift register 18B can be used to store four different types of the operational statuses for a second terminal. Data that represents the operational statuses for the respective terminals are provided to the data register circuit 12 in a series manner from the interface circuit 10 with reference to the first clock 14. Therefore, the display circuit 20 that cooperates with the first and second shift registers 18A and 18B can be used to display the related operational statuses of the first and second terminals via the display units 24. When the display units 24 are LEDs, the way for displaying the operational statuses of the terminals is to emit or to dim the light of the LEDs.
Please refer to FIG. 2. FIG. 2 is a timing diagram illustrating the relationship between the conventional first clock 14 with the conventional sequential data signal 16, both being outputted from the interface circuit 10. The horizontal axis of FIG. 2 represents time. With reference to the eight register units 19 in the data register circuit 12, one set of data 26 in the sequential data signal 16 has eight bits 16A, 16B, 16C, 16D, 16E, 16F, 16G, 16H. Among the data 26, the bits 16A to 16D are high-order (most significant) bits 26B, and the bits 16E to 16H are low-order (least significant) bits 26A. Furthermore, corresponding to each of the bits in the data 26, the first clock 14 also has eight corresponding clock periods 14A, 14B, 14C, 14D, 14E, 14F, 14G, 14H. Each of the clock periods has a period of T and is used to trigger operations of the first and second shift register 18A and 18B.
Please refer to FIGS. 3A to 3D. FIGS. 3A to 3D are schematic diagrams illustrating the operations of the conventional data register circuit 12 with the trigger of the first clock 14 at different clock periods. For clarity of description, the situation of storing the data 26 of FIG. 2 into the data register circuit 12 is taken as an example. The first register unit in the first shift register 18A is designated as the register unit 19A, and the second register unit in the first shift register 18A is designated as the register unit 19B. According to this designation, the register unit positioned at the right most side of the second shift register 18B is designated as the register unit 19H. The eight bits 16A to 16H of the data 26 have respective content of 1, 0, 1, 0, 0, 1, 1, 0, corresponding to the clock periods 14A to 14H of the first clock 14, respectively.
As shown in FIG. 3A, when the clock period 14A of the first clock 14 triggers the data register circuit 12, both of the first and second shift register 18A and 18B shift each of the bits in the respective register units 19 one bit right. Thus, the register unit 19A in the first shift register 18A is filled in with the first bit 16A of the data 26, and the numeral 23 is used to represent the content of the bit 16A. As shown in FIGS. 3A to 3D, arrows 28 are used to represent the movements toward the right-hand side for each of the bits in the data register circuit 12, and a symbol X is used to represent data stored in each of the register units 19 before the data 26 is shifted into the data register circuit 12. As shown in FIGS. 2 and 3A, the bit 16A is the first transferred bit in the data signal 16.
As time goes by, each of the clock periods of the first clock 14 triggers the first and second shift registers 18A and 18B to shift the content in each of the register units 19 to the respective adjacent right register unit 19 so as to store the bits of the data 26 successively. As shown in FIG. 3B, at the clock period 14B, the two bits 16A and 16B of the data 26 have been stored in the data register circuit 12. The bit 16A, which was originally stored in the register unit 19A of the first shift register 18A, is shifted to the register unit 19B according to the trigger of the clock period 14B. Then, the bit 16B of the data 26 is stored in the register unit 19A.
As shown in FIG. 3C, at the clock period 14E, the first five bits of the data 26 have been sequentially stored in the data register circuit 12 in time order of 16A, 16B, 16C, 16D, and 16E. The content of the bits 16A to 16E, which is 1, 0, 1, 0, 0, respectively, has been arranged in the left five register units of the data register circuit 12 from the right to the left. Finally, as shown in FIG. 3D, at the clock period 14H, all of the eight bits of the data 26 have been stored in the data register circuit 12 completely. The first transferred bit 16A of the data 26 is stored in the register unit 19H positioned at the most right-hand side of the second shift register 18B, and the last transferred bit 16H of the data 26 is stored in the register unit 19A positioned at the most left-hand side of the first shift register 18A.
According to the prior art, each of the bits of the data 26 is transferred in a series manner. The advantage of the prior art is that the circuit structure is more simplified. As shown in FIG. 1, the interface circuit 10 can utilize only one output end, which is typically a pin in a circuit, to output each of the bits of the data 26 sequentially. The layout of the interface circuit 10 thus can be considerably concise.
Nevertheless, whenever the content of the data 26 is changed, each of the bits of the data 26 is required to be re-transferred sequentially into the data register circuit 12. For example, when the content of the high-order bits 26B in the data 26 is changed from 1010 to 0011, although the content of the other four low-order bits 26A stored in the first shift register 18A is kept the same, the entire contents of the data 26, i.e., 00110110, is required to be re-transferred to the data register circuit 12 using duration of the eight clock periods according to the prior art. Particularly, since the high-order bits 26B of the data 26 have to be stored in the second shift register 18B through the first shift register 18A, when the data in the high-order bits 26B is updated, all of the bits in the data 26 have to be re-transferred from the prior art interface circuit 10 so as to update the data 26 in the data register circuit 12.
As previously described, the data register circuit 12 could be used in a network switch to display communications statuses for each terminal connected to the network switch by using a plurality of the display units 24. When the prior art data register circuit 12 is utilized in the network switch, the above-mentioned disadvantages will be more obvious. Typically, there is a possibility that only one specific status for a terminal among a plurality of terminals connected to the network switch is required to update. However, according to the prior art, to change the bit representing the specific status of the terminal in the data register circuit 12, all of the statuses of the terminals connected to the network switch are required to update simultaneously, even though the statuses of other terminals have not changed.
Furthermore, the data register circuit 12 having the eight register units 19 and the eight corresponding display units 24 shown in FIG. 1 is only a simplified example. In modern information applications, a terminal normally has four to eight statuses to be monitored, that is, a terminal has to be equipped with four to eight display units and the corresponding amount of register units. Generally, the network switch has to monitor more than ten terminals simultaneously. For displaying all of the statuses of the terminals, the data register circuit 12 has to be equipped with hundreds of the display units 24 and the corresponding amount of the register units 19. When only one status of a terminal is changed, each of the bits in the data register circuit 12 has to be shifted sequentially. In other words, a duration of hundreds of the clock periods is needed, and the update procedure wastes a considerable amount of time.
In past, if one desires to reduce the duration of the hundreds of clock periods, then the frequency of the clock must be increased. However, when the frequency of the clock is increased, the data register circuit 12 has to be re-designed into a high-frequency circuit for adapting to the high-frequency clock. Furthermore, the design, production, and fabrication of the high-frequency circuit are more expensive and time-consuming than the general circuit. Moreover, the conventional sequential update architecture of the data register circuit frequently has the disadvantage of signal flickering on the display units when operating at a higher frequency. Under this situation, taking the register unit 19A in FIG. 3 as an example, when the data signal is updated, all of the bits in the data signal are required to shift into the data register circuit 12 through the register unit 19A. Hence, during the movements of all of the bits in the data signal, the content of the register unit 19A is continuously changed. Consequently, the display unit 24 for displaying the data in the register unit 19A is continuously flickering. Accordingly, the life of the display unit 24 is reduced and the user monitoring the statuses of the display unit 24 feels uncomfortable. Because of this, erroneous judgment of the status of the display unit 24 will occur unexpectedly.
It is therefore a primary objective of the claimed invention to provide a signal display apparatus and a method for storing data to solve the above-mentioned problem.
According to the claimed invention, a signal display apparatus comprises a plurality of shift registers and a selecting circuit. The shift registers are used to receive a first clock. The selecting circuit is used to receive a selecting signal of a data flow according to a second clock, and output enabling signals to the shift registers according to the selecting signal. The shift registers selectively store data in the data flow according to the first clock for responding to the enabling signal.
It is an advantage of the claimed invention that the signal display apparatus and the method for storing data are capable of substantially reducing the transferring time for each bit of a single series signal to overcome the prior art shortcomings.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.